CMOS Fabrication

Step -1: Si substrate 

Start with P- type substrate.

Step - 2: Oxidation
Exposing to high purity Oxygen and silicon at approx 1000^oC in oxidation furnace.

Step - 3: Photo resist Coating
Photo resist is a light sensitive organic polymer softens when exposed to light.

Step - 4: Masking
Expose photo resist through N-well mask.

Step -5: Removal of Photo resist
Photo resist are removed by treating the wafer with acid or base solution.

Step - 6: Acid Etching
SiO2 is selectively removed from areas of wafer that are not covered by photo resist by using hydrofluoric acid.

Step - 7: Removal of Photo resist
Strip off the remaining photo resist.

Step - 8:Formation of N-well
N-well if formed with diffusion or ion implantation.

Step - 9: Removal of SiO2
Strip off the remaining oxide using HF

Step - 10: Polysilicon deposition

Deposit very thin layer of gate oxide using Chemical Vapor Deposition  (CVD) process.

Step - 11: N-Diffusion
N-Diffusion forms nMos source, drain, and n-well contact.

Oxidation

Masking

Dopants were diffusied or ion implanted.

Diffusion

Strip off oxide.

Step - 12: P - Diffusion
Similar set of steps form p+diffusion regions for pmos source, drain and substrate contact.

Step - 13: Contact cuts
The devices are to be wired together.
Cover chip with thick field oxide.
Etch oxide where contact cuts are needed.

Step - 14: Metallization:
Sputter on aluminium over whole wafer.
Pattern to remove excess metal, leaving wires.

Concepts MOS technology

Why PMOS is slower than NMOS?

The mobility of electron is more than mobility of hole. Basically free holes are present in valance band along with covalant bonds and free electrons are only present in conduction band. So free holes require more electric field to migrate as like free electrons. Because density of valance band is more than the conduction band. As PMOS having majority carriers are holes and NMOS having majority carriers are electrons these are the reasons behind speed of PMOS, NMOS.

Why CMOS is preferred over NMOS, PMOS?

In NMOS, PMOS short circuit current is flowing from VDD to GROUND for particular logic 

( nmos - logic '1', pmos - logic '0' ). So high static power is consumed on those logic's. But in CMOS short circuit current flows when both PMOS and NMOS transistors are in saturation region. This region will be very short span of time. Hence very less amount of static power will consume.

Inverter region of operation :

In this region of operations we can observe that in above diagram in one state the both PMOS and NMOS both are in the saturation region means in this state the both are in ON state. Due to this the short circuit current will flow directly from source (Vdd) to the ground (Vss) this is called as the leakage power in the CMOS.
The leakage power will be more if the input given has the high transition then the power dissipation will be more. To reduce the power dissipation the input shouldn't have high transition.

MOS Capacitor:

The MOS capacitor consists of Metal Oxide Semiconductor structure as shown. The semiconductor substrate with a thin oxide layer and a top metal contact, referred to as the gate. A second metal layer forms a  Ohmic contact to the back of the semiconductor and is called the bulk contact. The structure shown has a p-type substrate.

To understand the different bias modes of an MOS capacitor we now consider three different bias voltages. One below flat band voltage (Vfb), second between the flat band voltage and the threshold voltage (Vt) and the finally one larger than the threshold voltage. These bias are called the accumulation, depletion and inversion mode of operation.

Accumulation mode: (Vg < Vfb)
Accumulation occurs when one applies a voltage less than the flat band voltage. The negative charge on the gate attracts holes from the substrate to the oxide semiconductor interface. Only a small amount of band bending is needed to build up the accumulation charge so that almost all of the potential variation is within the oxide.

Depletion mode: (Vfb < Vg < Vt)
As a more positive voltage than the flat band voltage is applied, a negative charge builds up in the semiconductor. Initially this charge is due to the depletion of the semiconductor starting from the oxide semiconductor interface. The depletion layer width further increases with increasing gate voltage.

Inversion mode: (Vt < Vg)
As the potential across the semiconductor increases beyond twice the bulk potential, another type of negative charge emerges at the oxide semiconductor interface: this charge is due to minority carriers, which form a inversion layer. As one further increases the gate voltage, the depletion layer width barely increases further since the charge in the inversion layer increases exponentially with the surface potential.

Advantages of CMOS :

• High input impedance : As technology shrinks, it can operate with with very low current (micro amperes). If current decreases then resistance increases ( R = V/I ).
• Low static power consumption.
• high packing density.
• high noise immunity.

Latch up

What is Latch-up:

Latch up is a condition where a low impedance path is formed between the power supply and ground. By this circuit will be damaged permanently.

To understand the concept of the latch up we need to see how the NPN and PNP transistor is formed and how it operates.

As an example, in PMOS (as per Ohms's law) when the input current is low and the input nwell resistance is high then the voltage drop across resistor will high. If the voltage drop is above 0.7 v this can forward bias the Q1 transistor then it will be ON. So the output current Ic is given back to the NMOS Q2 transistor, here the input base current of the Q2 transistor is high and the input resistance is low, the drop occurred at the Q2 transistor makes ON. The output will be in the positive feed back loop this can increase the current abruptly in the circuit.  

Temperature effects (external and internal to the product) can also influence the Latch-Up immunity of products. As temperature increases, the substrate and well resistances rise allowing the bias to reach a critical value sooner. Also, the effective distance between the N+, P+ and N-Well diffusion narrows allowing easier capture of excited carriers.

                                                                  Q1- PNP transistor

                                                                  Q2- NPN transistor

                                       when Q1 (VBE >= 0.7 turns ON ), Ic= beta1 * Ib.

              The Ic current is given as input to Q2 then if it is more than VBE Q2 turns ON.

                                             The  output current (Ic) = beta2 * ( beta1 * Ib)

If beta1 * beta2 >= 1 both transistors conduct high saturation current will flow in the circuit. This damages the device. 

How to avoid Latch up condition:

1. Guard rings act as injected carrier syphons allowing these carriers to flow to the supply or ground. The Guard rings are placed around the CMOS, the spike which makes the PNP transistor turn ON that potential is absorbed by the Guard ring and it does not allow the PNP transistor to ON.

2. The resistance due to the well can be avoided by keeping parallel wire, this makes the potential spike which is occurred at the resistor will not make the Transistor to ON. 

Basics of VLSI

Introduction:

Invention of the transistor was the driving factor of growth in the VLSI technology. Before we get to know about the VLSI technology, let us have a basic knowledge of ELECTRONICS evolution. Electronics deals with circuits which involves active and passive components. These circuits are used in various Electronics Devices and are called Electronic Circuits.The components used in Electronic circuits are Diodes, Transistors, MOSFET'S. In the VLSI we will mainly concentrate on three factors they are: 1. AREA  2. POWER  3. TIMING.

Integrated Circuit:

Integrated Circuit is the circuit in which all the Passive and Active components are fabricated onto a single chip. Initially the Integrated Chip could accommodate only a few components. As the days passed, the devices became more complex and required more number of circuits which made the devices look bulky. Instead of accommodating more circuits in the system, an integration technology was developed to increase the number of components that are placed on a single chip. This technology not only helped to reduce the size of the devices but also improved the speed depending on the number of components to be integrated, they are categorized as SSI, MSI, LSI, VLSI, ULSI.

Small Scale Integration (SSI):
In this technology, 1-100 transistors were fabricated on a single chip, eg: Gates, Flip flops.

Medium Scale Integration (MSI):
Using this technology 100-1000 number of transistors could be integrated on a single chip. Eg: 4-bit micro processor.

Large Scale Integration (LSI):
Using this technology, 1000-10000 transistors could be integrated on a single chip. Eg: 8 bit Micro processor, RAM, ROM.

Very Large Scale Integration (VLSI):
In this technology, 10000-1 Million transistors could be accommodated. Eg: 16-32 bit Micro processors.

Ultra Large Scale Integration (ULSI):
In this technology, 1 Million- 10 Million transistors could be accommodated. Eg: Special Purpose Registers.

Moore's Law:

In 1965, Gordon Moore, an industry pioneer predicted that the number of transistors on a chip doubles every 18 to 24 months. He also also predicted that semiconductor technology will double its effectiveness every 18 months and many other factors grows exponentially.

Advantages of VLSI:

1. Higher Reliability

2. Increase the Operating speed of the circuit

3. Requires less power.

4. Reduces the size of the chip.