Concepts MOS technology

Why PMOS is slower than NMOS?

The mobility of electron is more than mobility of hole. Basically free holes are present in valance band along with covalant bonds and free electrons are only present in conduction band. So free holes require more electric field to migrate as like free electrons. Because density of valance band is more than the conduction band. As PMOS having majority carriers are holes and NMOS having majority carriers are electrons these are the reasons behind speed of PMOS, NMOS.

Why CMOS is preferred over NMOS, PMOS?

In NMOS, PMOS short circuit current is flowing from VDD to GROUND for particular logic 

( nmos - logic '1', pmos - logic '0' ). So high static power is consumed on those logic's. But in CMOS short circuit current flows when both PMOS and NMOS transistors are in saturation region. This region will be very short span of time. Hence very less amount of static power will consume.

Inverter region of operation :

In this region of operations we can observe that in above diagram in one state the both PMOS and NMOS both are in the saturation region means in this state the both are in ON state. Due to this the short circuit current will flow directly from source (Vdd) to the ground (Vss) this is called as the leakage power in the CMOS.
The leakage power will be more if the input given has the high transition then the power dissipation will be more. To reduce the power dissipation the input shouldn't have high transition.

MOS Capacitor:

The MOS capacitor consists of Metal Oxide Semiconductor structure as shown. The semiconductor substrate with a thin oxide layer and a top metal contact, referred to as the gate. A second metal layer forms a  Ohmic contact to the back of the semiconductor and is called the bulk contact. The structure shown has a p-type substrate.

To understand the different bias modes of an MOS capacitor we now consider three different bias voltages. One below flat band voltage (Vfb), second between the flat band voltage and the threshold voltage (Vt) and the finally one larger than the threshold voltage. These bias are called the accumulation, depletion and inversion mode of operation.

Accumulation mode: (Vg < Vfb)
Accumulation occurs when one applies a voltage less than the flat band voltage. The negative charge on the gate attracts holes from the substrate to the oxide semiconductor interface. Only a small amount of band bending is needed to build up the accumulation charge so that almost all of the potential variation is within the oxide.

Depletion mode: (Vfb < Vg < Vt)
As a more positive voltage than the flat band voltage is applied, a negative charge builds up in the semiconductor. Initially this charge is due to the depletion of the semiconductor starting from the oxide semiconductor interface. The depletion layer width further increases with increasing gate voltage.

Inversion mode: (Vt < Vg)
As the potential across the semiconductor increases beyond twice the bulk potential, another type of negative charge emerges at the oxide semiconductor interface: this charge is due to minority carriers, which form a inversion layer. As one further increases the gate voltage, the depletion layer width barely increases further since the charge in the inversion layer increases exponentially with the surface potential.

Advantages of CMOS :

• High input impedance : As technology shrinks, it can operate with with very low current (micro amperes). If current decreases then resistance increases ( R = V/I ).
• Low static power consumption.
• high packing density.
• high noise immunity.