Latch up

What is Latch-up:

Latch up is a condition where a low impedance path is formed between the power supply and ground. By this circuit will be damaged permanently.

To understand the concept of the latch up we need to see how the NPN and PNP transistor is formed and how it operates.

As an example, in PMOS (as per Ohms's law) when the input current is low and the input nwell resistance is high then the voltage drop across resistor will high. If the voltage drop is above 0.7 v this can forward bias the Q1 transistor then it will be ON. So the output current Ic is given back to the NMOS Q2 transistor, here the input base current of the Q2 transistor is high and the input resistance is low, the drop occurred at the Q2 transistor makes ON. The output will be in the positive feed back loop this can increase the current abruptly in the circuit.  

Temperature effects (external and internal to the product) can also influence the Latch-Up immunity of products. As temperature increases, the substrate and well resistances rise allowing the bias to reach a critical value sooner. Also, the effective distance between the N+, P+ and N-Well diffusion narrows allowing easier capture of excited carriers.

                                                                  Q1- PNP transistor

                                                                  Q2- NPN transistor

                                       when Q1 (VBE >= 0.7 turns ON ), Ic= beta1 * Ib.

              The Ic current is given as input to Q2 then if it is more than VBE Q2 turns ON.

                                             The  output current (Ic) = beta2 * ( beta1 * Ib)

If beta1 * beta2 >= 1 both transistors conduct high saturation current will flow in the circuit. This damages the device. 

How to avoid Latch up condition:

1. Guard rings act as injected carrier syphons allowing these carriers to flow to the supply or ground. The Guard rings are placed around the CMOS, the spike which makes the PNP transistor turn ON that potential is absorbed by the Guard ring and it does not allow the PNP transistor to ON.

2. The resistance due to the well can be avoided by keeping parallel wire, this makes the potential spike which is occurred at the resistor will not make the Transistor to ON.