Basics of CMOS

MOSFET:

The MOS transistor, also called MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or IGFET (Insulated-Gate Field-Effect Transistor) is the most widely used semiconductor device and is at the heart of every digital circuit. Without the MOSFET there would be no computer industry, no digital telecommunication systems, no video games, no pocket calculators and no digital wristwatches. MOS transistors are also increasingly used in analog applications such as switched capacitor circuits, analog-to-digital converters, and filters.

The exponential progress of MOS technology is best illustrated by the evolution of the number of MOS transistors integrated in a single memory chip or single microprocessor, as a function of calendar year. Each memory cell of a dynamic random-access memory (DRAM) contains a MOS transistor and a capacitor. This exponential growth of integration density with time is known as Moore's law.

The integration density of memory circuits is about 5 to 10 times higher than that of logic circuits such as microprocessors because of the more repetitive layout of transistors in memory chips. The increase in integration density is essentially due to the reduction of transistor size.

There are two types of MOS transistors: n-channel MOSFET, p- channel MOSFET.
N-channel MOSFET: The n-channel MOSFET in which current flow is due to electron transport, and the p-channel MOSFET in which holes are responsible for current flow. A circuit containing only n-channel devices is produced by an nMOS process.

Similarly, a pMOS process fabricates circuits that contain only p-channel transistors. Today the most commonly used technology is CMOS (Complementary MOS) in which both n-channel and p-channel transistors are fabricated. Here we will limit our analysis to n-channel devices. The current-voltage expressions describing a p-channel device can readily be derived from the n-channel equations, provided the appropriate changes of sign are made. An n-channel MOS transistor is fabricated in a P-type semiconductor substrate, usually silicon. Two N-type diffusions are made in the substrate and the current flow will take place between these two diffusions. The diffusion with the lowest applied potential is called the "source" and the diffusion with the highest applied potential is called the "drain". Above the substrate, and between the source and the drain lies a thin insulating layer, usually silicon dioxide, and a metal electrode called "gate". An electron-rich layer referred to as the "channel" can be created between the source and the drain underneath the gate insulator when a positive bias is applied to the gate. With appropriate voltages applied at the source and drain electrons can then flow from the source into the drain, through the channel.

P-channel MOSFET:
In a p-channel transistor an N-type substrate is used. The P-type drain is at a lower potential than the P-type source and the application of a negative bias to the gate enables the formation of a hole-enriched channel between source and drain. The metal-insulator semiconductor structure is often referred to as a "MIS" structure, where the "I" stands for the insulator. When the insulator is an oxide, it is called a "MOS" structure.

OPERATION OF N-CHANNEL MOSFET:

The basic operation of the n-channel MOSFET is the following. We will first consider the case where the gate voltage is equal to zero while the P type substrate and the source are grounded The drain is connected to a positive voltage source for instance). Since the source and the substrate are at the same potential there is no current flow in the source-substrate junction. The drain-substrate junction is reverse biased and except for a small negligible reverse leakage current no current flows in that junction either. Under these conditions there is no channel formation, and therefore, no current flow from source to drain. In the second case a constant positive bias is applied to the gate. There is no gate current since the metal electrode is dielectrically insulated from the silicon. Because it is positively biased the gate electrode does, however, attract electrons from the semiconductor, and a thin, electron rich layer forms under the gate insulator. These electrons are supplied by the source and the drain which, being N-type, are large reservoirs of electrons. The electron-rich layer underneath the gate is called "channel". The N-type source and the N-type drain are connected by the electron rich channel, and current is now free to flow between source and drain. The effect of the gate voltage controlling the concentration of electrons in the semiconductor through the gate oxide is called "field effect". The bias on the gate creates an electric field which can either induce or inhibit the formation of an electron-rich region at the surface of the semiconductor. The terms "source", "drain", "channel" and "gate" come to mind quite naturally since the electrons originate at the source, flow through the channel and are finally collected by the drain, the whole process being controlled by the bias on the gate.

In the above equations "lamda" is Channel length modulation.

 

Body effect :
Body effect is major drawback of CMOS technology. This will effect when substrate or body not biased with source. There is PN-juction diode present in between substrate and source so this will effect the change of threshold voltage. in order to avoid this effect we have to give same potential to both substrate and source.
In Body effect when we give the supply voltage to the gate (+ ve) and source to (- ve) at this condition there will be formation of a diode in the reverse bias this will increase the depletion region this makes the decreasing the channel and the threshold voltage will also increases, so in order to maintain the channel we need to increase the gate voltage.
Due to this effect we are biasing the source and substrate to the same potential which will not allow the moment of depletion towards the gate by this the Threshold voltage will not be increased.

Channel Length Modulation :

To understand the Channel length modulation, first we need to know about pinch-off of the channel is introduced. The channel is formed by attraction of carriers to the gate and the current  drawn through the channel is nearly a constant independent of drain voltage in saturation mode.

As the drain voltage increases, its control over the current extends further towards source, so the uninverted region expands towards the source, shortening the length of the channel region. The effect is called Channel Length Modulation. Because resistance is proportional to length, shortening the channel decreases its resistance, causing an increase in current with increase in drain bias for a MOSFET operating in saturation region.

Short Channel Effects

The main drives for reducing the size of the transistors like their lengths, it increases speed and reducing cost. When you make circuits smaller, their capacitance's reduces, thereby increasing operating speed. In short channel there is a two - dimensional potential distribution and high electrical fields in the channel region.
  However, with great reduction of the channel there arises of short channel effects. For a given channel doping concentration, as channel length is reduced, the depletion layer widths of the source and drain junctions become comparable to the channel length. The potential distribution in the channel depends on both the traverse field ( controlled by the gate voltage ) and the longitudinal field ( controlled by the drain bias ).  When the channel of the MOSFET becomes the same order of magnitude as the depletion layer width of source and drain, the transistor start behaving differently, which impacts the performance and reliability.

The Short Channel Effects are:
1. Mobility Degradation
2. Sub-threshold current
3. Drain Induced Barrier Lowering (DIBL)
4. Surface Scattering
5. Velocity Saturation
6. Impact Ionization
7. Hot Carrier Injection

Mobility Degradation:

Mobility is important because the current in the MOSFET depends upon the mobility of charge carriers ( electrons and holes ).

The mobility can be degraded by two effects:
1. Lateral Field Effect: In short channels, as lateral field is increased, the channel mobility becomes field dependent and velocity saturation occurs. This results in current saturation.
2. Vertical Field Effect: As the vertical electric field also increases on shrinking the channel lengths, its results in scattering of carriers near the surface. Hence the surface mobility reduces.

Thus for short channels, the mobility degradation which occurs due to velocity saturation and scattering of carriers.

Sub-Threshold Current:

The sub threshold current always flows from source to drain even if the gate to source voltage is lesser than the threshold voltage of the device. This happens due to carrier diffusion between the source and drain regions of the CMOS transistor in weak inversion. When gate to source voltage is smaller than threshold voltage then leakage current will flow because of the minority charge carriers in the substrate. That makes the small current will flow from source to drain and becomes significant in the Lower Technology nodes.

Drain Induced Barrier Lowering (DIBL):

The drain potential on the channel region can have serious impact on the performance of sub-micron MOS transistors. One effect that is very similar to the punch-through effect is Drain-Induced Barrier Lowering (DIBL). In some of the books punch-through is sometimes referred to as ``subsurface DIBL'' in contrast to ``surface DIBL''.

In the weak inversion region there is a potential barrier between the source and the channel region. The height of this barrier is a result of the balance between drift and diffusion current between these two regions. If a high drain voltage is applied, the barrier height can decrease, leading to an increased drain current. Thus the drain current is controlled not only by the gate voltage, but also by the drain voltage.

For better understanding, under normal conditions when (Vds=0 and Vgs=0), there is a potential barrier that stops the electrons flow from source to drain. The gate has the function of lowering this barrier down to the point where electrons able to flow from source to drain. Ideally, the gate voltage only that would affect the barrier. As the channel becomes shorter, a larger Vd widens the drain depletion region to a point that reduces the potential barrier.

As the drain is close enough to source to easily form the depletion region normally created by the gate. That is, the drain depletion region extends to source, forming a unique depletion region this is known as punch-through.

Surface Scattering:

As the channel length becomes smaller due to the lateral extension of the depletion layer into the channel region, the longitudinal electric field component increases, and the surface mobility becomes field-dependent. Since the carrier transport in a MOSFET is confined within the narrow inversion layer, and the surface scattering (that is the collisions suffered by the electrons that are accelerated toward the interface) causes reduction of the mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of, is about half as much as that of the bulk mobility.

Velocity Saturation:

The performance short-channel devices is also affected by velocity saturation, which reduces the trans-conductance in the saturation mode. At low Ey, the electron drift velocity Vde in the channel varies linearly with the electric field intensity. However, as Ey increases above 104 V/cm, the drift velocity tends to increase more slowly, and approaches a saturation value of Vde (sat) = 107 cm/s around Ey = 105 V/cm at 300 K. Note that the drain current is limited by velocity saturation instead of pinchoff. This occurs in short channel devices when the dimensions are scaled without lowering the bias voltages.

Impact Ionization:

Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocity of electrons in presence of high longitudinal fields that can generate electron-hole (e-h) pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them. It happens as follow: normally, most of the electrons are attracted by the drain, while the holes enter the substrate to form part of the parasitic substrate current. Moreover, the region between the source and the drain can act like the base of an NPN transistor, with the source playing the role of the emitter and the drain that of the collector. If the aforementioned holes are collected by the source, and the corresponding hole current creates a voltage drop in the substrate material of the order of 0.6 V, the normally reversed-biased substrate-source PN junction will conduct appreciably. Then electrons can be injected from the source to the substrate, similar to the injection of electrons from the emitter to the base. They can gain enough energy as they travel toward the drain to create new eh pairs. The situation can worsen if some electrons generated due to high fields escape the drain field to travel into the substrate, thereby affecting other devices on a chip.

Hot Carrier Injection:

The channel Hot Carrier effect is caused by electrons flowing in the channel for large Vds. Electron arriving at the Si-Sio2 interface with enough kinetic energy > 3.1eV to surmount the surface potential barrier are injected into the oxide. This may degrade permanently the C-V characteristics of MOSFET's.

Note: The channel hot-electron current and the subsequent damage in the gate oxide are localized near the drain junction.

The hot carrier electron induced damage in NMOS transistors has been found to result in either trapping of carriers on defect sites in the oxide or the creation of interface states at the silicon-oxide interface, or both.
The damage caused by hot carrier injection affects the transistor characteristics by causing a degradation in trans-conductance, a shift in the threshold voltage, and a general decrease in the drain current capability.